1. Technical Field
The present invention relates to a memory control circuit and a memory control method.
2. Description of the Related Art
FIG. 21 depicts a configuration of a typical memory. A memory 50 can read and write up to L bits of data specified by an A-bit address. Two methods are conceivable to store various data with different data widths as shown in FIG. 22 into the memory 50.
In one method, as shown in FIG. 23, each piece of data is stored at one address (see, e.g., Japanese Patent Application Laid-Open Publication No. 1994-266614). In the other method, as shown in FIG. 24, a plurality of data with different data widths is packed into the memory 50.
However, if the method shown in FIG. 23 is used, when storing data with a data width less than L bits, an unused data area (invalid data area) is generated, which deteriorates the usage efficiency of the memory. If the method shown in FIG. 24 is used, although the invalid data area is not generated and the usage efficiency of the memory 50 is improved, processes of packing and unpacking data are needed before writing data into the memory 50 and after reading data from the memory 50, which increases a processing load.